Gate length scaling of gate-all-around (GAA) field-effect transistors (FETs) with nanowire channels can be achieved provided that the nanowire channel diameter can be reduced. For example, scaling of a GAA metal-oxide semiconductor field-effect transistor (MOSFET) to sub-20 nanometer (nm) gate length requires nanowire channels with a diameter of less than 10 nm. See, for example, Oh et al., “Analytic Description of Short-Channel Effects in Fully-Depleted Double-Gate and Cylindrical, Surrounding-Gate MOSFETs,” Electron Dev. Lett., vol 21, no. 9, pgs. 445-47 (2000). Fabricating nanowires at this scale with current lithographic capabilities introduces large variations, both in nanowire size and in line edge roughness (LER). The scale of these variations can be a significant fraction of the nanowire size, and can thus lead to perturbations in the channel potential and scattering that degrade the charge transport characteristics. Additionally, variations in the nanowire diameter induce variations in the FET's threshold voltage.
In many instances the size of the nanowires needs to be reduced further to dimensions smaller than current lithographic methods can produce. Thinning of the nanowire body is commonly achieved by thermal oxidation. However, the oxidation rate of nanowires can be substantially slower than planar silicon (Si), with the oxidation rate dropping with smaller diameter nanowires. See, for example, Liu et al., “Self-Limiting Oxidation for Fabricating Sub-5 nm Silicon Nanowires,” Appl. Phys. Lett., 64(11), pgs. 1383-1385 (1994). As such, the oxidation time required for thinning of nanowires can undesirably result in the complete oxidation of the planar Si in the source and drain regions. To avoid oxidation of the source and drain regions most methods use an oxidation blocking mask to protect these regions. The blocking mask needs to be aligned and patterned such that it will cover the source and drain regions but leave the nanowires exposed. Stress in the mask can lead to an uneven oxidation at the mask's edge, which leads to non-uniform thinning of the nanowires.
In view of the foregoing, there is a need for techniques that form thin nanowires with good dimensional control and very low LER. The required nanowires dimension may be smaller than can be defined by lithographic techniques, so thinning of the nanowires may be needed. The thinning method needs to reduce the diameter of the nanowires without thinning the planar source and drain regions to which the nanowires are attached. Preferably, the thinning method should be mask-less for simplicity and cost reduction, and to avoid uneven thinning that typically occurs at the mask edges.